The present invention relates generally to semiconductor fabrication and more specifically to, the fabrication of field effect transistors (FETs) having an asymmetrical structure.
In a typical replacement gate process for manufacturing a FET, a dummy gate is lithographically formed on the substrate, spacers are formed on the sidewalls of the dummy gate, and a dielectric is deposited to cover the gates and fill the areas between gates. The dielectric is then polished or etched back so as to be co-planar with the dummy gate. Then the dummy gate is removed leaving an opening in the dielectric. Within the opening, a gate dielectric is deposited and the remainder of the opening is over-filled with gate material. The structure is then polished so that the gate material in the opening and the dielectric are co-planar.
The drive for high performance requires high speed operation of microelectronic components requiring high drive currents in addition to low leakage, i.e., low off-state current, to reduce power consumption. In conventional transistor technologies, the source/drain extensions may overlap the gate region of the device. This overlap causes overlap capacitance in the device. In general, the greater the overlap of the source/drain extensions with the gate region, the greater the overlap capacitance is. In current FET configurations, the amount of overlap of a source extension with a gate region is approximately equal to the amount of overlap of a drain region extension with the gate region.